Physical Design Engineer - Synthesis & Floorplanning in Sunnyvale
Job Description
Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-, Regional IT Service Provider. Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.
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We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.
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Key Responsibilities
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- Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals
- Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution
- Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation
- Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency
- Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence
- Support timing closure by identifying implementation bottlenecks and recommending design improvements
- Participate in design reviews and contribute to continuous process and methodology improvements
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Required Qualifications
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- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Strong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience.
- Expertise in RTL synthesis and timing optimization
- Solid experience with floorplanning for advanced technology nodes
- Strong understanding of netlist optimization and physical implementation methodologies
- Experience collaborating with RTL/design teams to improve design quality and implementation efficiency
- Excellent communication and cross-functional collaboration skills
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Skills
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- Experience with industry-standard EDA tools for synthesis and physical design
- Strong understanding of timing, congestion, power, and area optimization techniques
- Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus
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