Formal Design Verification Engineer in San Jose

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Job Description

We are looking for candidates with most recent hands-on experience in formal verification.

Required Skills:

• Minimum of 3yrs experience (most recent experience in formal verification) & NOT looking for anyone with more than 10yrs.
• Hands-on System Verilog Assertion coding for formal setups
• Hands-on experience with equivalence checking, C & RTL model checking and feature verification setups in Formal
• Exposure to VC Formal or Jasper Gold tool
• Most recent experience in Formal verification

If you are interested in applying for this job please press the Apply Button and follow the application process. Energy Jobline wishes you the very best of luck in your next career move.