Field-Programmable Gate Arrays Engineer in San Jose

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Job Description

We are hiring an FPGA Engineer with 5–6 years of experience in RTL design and verification.

Location: San Jose / Santa Clara, CA

Duration: 12-month contract

Key Responsibilities:

• Develop RTL using Verilog/SystemVerilog

• Perform simulation, debugging, and testing

• Support FPGA bring-up and hardware integration

Required Skills:

• Hands-on experience with FPGA tools (Xilinx or Intel/Altera)

• Strong background in RTL design and verification

• Experience with debugging and end-to-end FPGA development

If you’re interested or know someone who fits this role, feel free to connect or share your resume.

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