Design Verification Engineer in Austin
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Job DescriptionJob Description
Verification Architect / Engineer - RTL design
Experience : 5 to 10 years
Location : USA - Austin
Employment Type: Full-time
Visa Sponsorship: H1-B Sponsorship Available
JOB DESCRIPTION :
About The Position
We are looking for a Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.
Youll be part of a pioneering company at the at the forefront of next-gen optical communication systems (800G, 1.6T, and beyond), working alongside seasoned industry leaders and engineers. This is an exceptional opportunity to influence the architecture of AI connectivity and shape the technologies driving modern data infrastructure.
Responsibilities
Plan, architect, and execute verification strategies for digital design blocks based on design specifications.
Develop and maintain verification environments using SystemVerilog and UVM
Define and implement comprehensive coverage metrics, including corner-case scenarios.
Debug RTL functionality in close collaboration with design and architecture teams.
Perform coverage collection, analysis, and closure to ensure full functional completeness.
Participate in design reviews, test plan creation, regressions, and sign-off activities.
Required Qualifications
5+ years of professional experience in digital/RTL engineering
At least 3 years of experience in design verification
In depth knowledge in VLSI verification flow, and concepts a must.
Deep understanding of VLSI verification flows, concepts, and industry-standard tools.
Proven experience completing at least one full block or system verification cycle.
Hands-on experience building verification environments using SystemVerilog + UVM, or equivalent frameworks (specman/eRM, SystemC).
Strong debugging skills and familiarity with waveform analysis tools.
Nice to Haves
Digital data-path or protocol-level verification, particularly Ethernet or related high-speed interfaces.
Experience writing advanced functional, code, and corner-case coverage.
Exposure to mixed-signal or analog/digital verification environments.
Strong communication skills, including writing test plans, documenting results, and presenting to cross-functional teams.
Must Have :
On-site in Austin, TX, five days a week.
5+ years of professional experience in digital/RTL engineering
At least 3 years of experience in design verification
In depth knowledge in VLSI verification flow, and concepts a must.
Deep understanding of VLSI verification flows, concepts, and industry-standard tools.
Proven experience completing at least one full block or system verification cycle.
Hands-on experience building verification environments using SystemVerilog + UVM, or equivalent frameworks (specman/eRM, SystemC).
Strong debugging skills and familiarity with waveform analysis tools.
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