ASIC Design Engineer- RTL

Recruiter
Location
England, Cheshire
Salary
competitive
Posted
30 Nov 2016
Closes
30 Dec 2016
Ref
PR-32505315
Contact
Elsa Naughton
Sector
Engineering
Category
Electrical
Contract Type
Contract
Hours
Full Time

Progressive Engineering arecurrently seeking a highly motivated and experienced ASIC Design engineer to work in validating block and system level IP.

Requirements

5+ years Industry Experience

RTL - Verilog
Mixed mode simulation - Cadence Based
Matlab
CPU Integration
Digital Filter Design
State Machine Design
Digital Place and Route (Virtuoso Digital Implementation) Digital Interface Design Low power digital techniques Scripting languages (e.g. perl)

To find out more about Progressive Recruitment please visit www.progressiverecruitment.com

Progressive Recruitment, a trading division of SThree Partnership LLP | Registered office | 1st Floor, 75 King William Street, London, EC4N 7BE, United Kingdom | Partnership Number | OC387148 England and Wales